The present invention relates generally to a method for forming metal lines in the manufacture of a highly integrated semiconductor device, and, more particularly, to a method for forming a metal line in which a diffusion barrier layer and a metal layer are formed at a high temperature in the range of 500.degree. C.-800.degree. C., and a sputtering apparatus therefor.
In general, the memory capacity of semiconductor memory devices (e.g., DRAMs) has quadrupled appoximately every four years. For example, 1 Mb DRAMs were in mass production approximately four years before 4 Mb DRAMs were in mass production, which were in mass production approximately four years before 16 Mb DRAMs were in mass production. At the present time, 64 Mb DRAMs are going into mass production, and 256 Mb DRAMs are still under development. As a result of this quadrennial quadrupling of memory capacity, and the commensurate increases in the integration density of such semiconductor devices, the minimum size of the geometries or features etched into the various layers of such semiconductor devices must be commensurately decreased (scaled down) in order to enable a much greater number of circuit elements, e.g., transistors, to be formed per unit of area of the device. The minimum size of the geometries or features, e.g., the channel length of the transistors, is referred to as the "design rule". For example, the minimum design rule for 1 Mb DRAMs approaches 1 .mu.m, the minimum design rule for 4 Mb DRAMs approaches 0.8 .mu.m, and the minimum design rule for 16 Mb DRAMs approaches 0.5 .mu.m. As a result of this progressive shrinkage of the geometries of semiconductor devices, the linewidth of aluminum lines thereof has commensurately decreased, thereby degrading the reliability and functionality of the aluminum lines, and thus, the reliability and operating speed of the devices. For example, problems which have accompanied decreases in the minimum design rule include electromigration due to high current density, degradation of shallow junction characteristics due to Al spiking of the silicon substrate, and increased contact resistance due to smaller ohmic contacts and increased contact hole aspect ratios.
One technique that has been developed to minimize the above-stated problems is to provide a diffusion barrier layer between the aluminum lines and the base layer, e.g., the semiconductor substrate. With reference now to FIGS. 1-4, a conventional method for forming a metal line using this technique will now be described.
With particular reference now to FIG. 1, an insulation layer (e.g., an oxide layer) 12 is formed on a silicon substrate 10. A contact hole is then formed in the oxide layer 12 by a conventional photolithographic etching process, to thereby expose a portion of the substrate 10. Next, an ohmic layer, e.g., a titanium layer 14, is formed on the oxide layer 12 and the exposed portion of the substrate 10, by a sputtering method. With reference now to FIG. 8A, which depicts the portion designated "a" in FIG. 1 in greater detail, an amorphous TiSi.sub.x layer 13 is formed between the titanium layer 14 and the substrate 10 as a consequence of the formation of the titanium layer 14.
With particular reference now to FIG. 2, a diffusion barrier layer, e.g., a titanium nitride layer 16, is formed on the titanium layer 14, by a sputtering method. Subsequently, the resultant structure is annealed in a furnace under a nitrogen atmosphere, at a temperature of 400.degree.-500.degree. C. The portion designated "b" in FIG. 2 can be seen in greater detail in FIG. 9A.
With particular reference now to FIG. 3, a metal, e.g., aluminum, is deposited on the titanium nitride (TiN) layer 16, by a sputtering method, to thereby form a metal layer 18 on the titanium nitride layer 16.
With particular reference now to FIG. 4, the metal layer 18 is heat-treated at a high temperature below its melting point, to thereby cause the metal layer 18 to reflow and fill the contact hole, thus providing a metal line layer 19. With reference now to FIG. 10A, which depicts the portion designated "c" in FIG. 4 in greater detail, it can be seen, that a TiON layer 17 is formed on the titanium nitride layer 16 as a consequence of oxidation which occurs during the annealing step.
Although the above-described conventional method for forming a metal line has achieved widespread use, it still suffers from significant drawbacks and shortcomings. First, the method is unduly complex, thereby increasing the cost and decreasing the reliability and efficiency of the semiconductor device manufacturing process. Second, because the Ti layer 14 is deposited by means of a sputtering process carried out at a low temperature of 200.degree. C. or below, the titanium and the silicon do not fully react with each other, with the consequence that the amorphous TiSi.sub.x layer 13 is formed between the Ti layer 14 and the substrate 10, which increases contact resistance. Third, since the annealing step is carried out at ambient atmospheric pressure, the TiN layer 16 is oxidized, thereby resulting in the formation of the TiON layer 17 on the TiN layer 16, which also increases contact resistance, and, further, degrades the quality of the metal layer 18 deposited thereon.
Based on the above, it can be appreciated that there presently exists a need in the art for a method for forming metal lines and a sputtering apparatus therefor which eliminates the above-described drawbacks and shortcomings of the presently available technology. The present invention fulfills this need.